In the process of manufacturing semiconductor memory devices it is desirable to improve product reliability by performing screening examinations of memory devices such as semiconductor chips. One goal of such an examination is to determine which memory devices, e.g. chips, are defective. Another goal of such an examination is to determine which memory devices (chips) include weak cells. A most commonly used technique for attempting to achieve this objective is to measure the rate of data retention while varying the data retention time. However, there is the disadvantage that measuring data retention times during screening examinations of memory chips is a very expensive process.
Another concern is that there is no way to determine the relevant characteristics of each memory cell within an array. For example there is a concern about cell capacitors, bitline capacitors and the relationship between a particular cell capacitor and a particular bitline capacitor during the development phase. Even if one can make that determination, the result must be achieved with a special test vehicle; not by a measurement from an actual memory array.
U.S. Pat. No. 4,468,759 of Kung, et al. entitled “Testing method and apparatus for DRAM” states in the abstract “A method for testing an MOS, dynamic random-access memory employing full capacitance dummy cells is described. During probe testing a potential higher than the reference potential is applied to the dummy cells when reading binary zeroes from the memory and a potential lower than the reference potential is applied to the dummy cells when reading binary zeroes from the memory. This testing procedure detects weak cells and amplifiers and helps present the packaging of defective parts. In addition, a simplified means for programming redundant elements is described which requires substantially less substrate area than previous methods.”
U.S. Pat. No. 5,544,108 of Thomann entitled “Circuit And Method For Decreasing the Cell Margin During a Test Mode” indicated that during a read mode when a first cell has been selected the first access transistor of the selected first cell actuates and couples the charge stored on the first storage capacitor of the first cell to its respective digit line. The charge stored in the first storage capacitor has a potential different than the potential of the digit line. This difference between the potential of the first storage capacitor and the potential of the digit line is the cell margin. The patent states further that “The N-sense amplifier senses the cell margin and determines what data has been stored in the cell. Next the N-sense amplifier amplifies the potential of the digit line to reflect the value of the potential stored in the cell. Once amplified the digit line in electrical communication with the selected cell has a potential representing the data bit stored in the storage capacitor, and the remaining digit line of the digit line pair has a potential equal to the complement of the data bit stored in the storage capacitor of the selected cell.”
In accordance with this invention, a dummy memory cell within a memory array is used to simulate or measure the cell data margin. Additional capacitors added to the bit line capacitor from the dummy memory cell will vary the capacitor ratio between a bitline capacitor and a cell storage capacitor. This leads to a change in the signal value developed at the bitline from the normal memory cell when the nominal cell wordline is selected. In this way, one can easily detect which cells are the weak cells at an early phase of product development before commencement of refresh testing or prior to shipping of commercial products.